DC-ROMA RISC-V Mainboard III, powered by the K3 SOC, is now available for hot pre-order

DC-ROMA RISC-V Mainboard III
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K3 DC-ROMA RISC-V Mainboard III, equipped with the K3 SOC, is now on hot pre-sale. The K3 SOC is the world’s first RISC-V AI SoC supporting the RVA23 profile. Please click the link below to check the pre-sale information: https://store.deepcomputing.io/products/dc-roma-risc-v-mainboard-iii-for-framework-laptop-13-early-access-program

FRAMEWORK LAPTOP_RISCV+Mainboar_1568x1568
FRAMEWORK LAPTOP_RISCV+Mainboar_1568x15681568×1568 207 KB

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Repost from Framework Forums of my brief research:

For more information about the chip (including the GPU), a overview can be found here (note this is the variant with 2 core clusters, DC seems to be using 1):

X100 Cores (CPU) have SPECint2006 ~9/GHz (it runs at 2.5GHz). Pretty ok score other RISC-V processors (e.g. XiangShan have ~15/GHz of SPECint2006, SiFive P800 ~18/GHz but both are also not available for purchase :rofl: )

For comparison in-house comparison, the cores in the DC ROMA II had an advertised score of 8.65/GHz. That did however run at 2.0 GHz, thus maybe a ~30% speed increase is expected. It seems the main selling point of this generation is the RVV support (which is indeed very exciting).

A100 Cores (AI accelerator) advertise support for 1024-bit RVV extension, and run at theoretically 30 TOPS (I would assume INT4?).

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(Various IPC of RISC chips)

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Hello,

I would like to ask a few questions regarding your **DC-ROMA III** board.

According to the documentation, the board includes the **Core SpacemiT K3** processor. In the K3 specifications, features such as **MIPI, Video Encoding/Decoding, CAN FD, and PCIe** are listed. Could you please clarify which of these interfaces are actually exposed and usable on the DC-ROMA III board design?

I also have a question regarding virtualization support. The K3 processor specification mentions support for the **RISC-V H extension (Hypervisor extension)**. Is this implemented as a hardware-supported hypervisor feature on the chip, or is the hypervisor functionality implemented purely through system software?

Additionally, could you please share a **detailed technical specification or datasheet** for the board?

Thank you for your time, and I look forward to your response.

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Thanks for your interest in our DC-ROMA K3 RISC-V mainboard. We have received your email and attempted to reply regarding your question. However, it appears that the email address you provided may not be functioning properly, as our replies could not be delivered. Below is reply to your questions:

  • For K3 features supported: the mainboard is in developing and testing phase by now, so we can not list all features the mainboard will support. But generally most features of the K3 chip will be supported in the mainboard too. Maybe you can preorder first as the order can be cancelled for free before it’s actual shipment.

  • The K3 fully supports RVA 23 profile and the RISC-V H extentsion is impleted in k3 chip lelvel (by X100 core) ,so it’s supported by hardware level, like RVH/AIA/IOMMU features.

You are welcome to preorder by our official store : https://store.deepcomputing.io/products/dc-roma-risc-v-mainboard-iii-for-framework-laptop-13-early-access-program

Feel free to contact us again using a valid email address at sales@deepcomputing.io/support@deepcomputing.io

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Thank you for quick response, maybe our university mail system had issue sorry about it.